1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM). More particularly, the present invention relates to a trench capacitor of a DRAM and fabricating method thereof.
2. Description of the Related Art
As semiconductor finally enters the deep sub-micron regime, the dimensions of each device are significantly reduced. This means that the area for accommodating the capacitors of a DRAM is correspondingly reduced. On the other hand, with the ever-increasing size of computer application software, the amount of memory needed to operate the software also increases at an alarming rate. Such conflicting demand for a smaller dimension and a larger memory storage capacity implies that the former method of fabricating the capacitors of a DRAM must be modified to fit this trend.
According to the structure of capacitor, the DRAM can be classified into two major types, namely, the stack capacitor DRAM and the deep trench capacitor DRAM. With the constant pressure for reducing the dimension of semiconductor devices, an increasing number of technical problems are encountered in the fabrication of both types of DRAM.
In general, a DRAM device comprises a plurality of memory cells. Each memory cell includes an active device region and a deep trench capacitor (as shown in FIG. 1). FIG. 1 is a schematic cross-sectional view showing the structure of a conventional DRAM. The DRAM comprises a substrate 100, a capacitor 102, an isolation structure 104, active devices 106a and 106b, doped regions 108, an insulating layer 110 and contacts 112a and 112b. The capacitor 102 is disposed in the substrate 100. The capacitor 102 further comprises a lower electrode 114, a capacitor dielectric layer 116 and an upper electrode 118. The isolation structure 104 is disposed in the substrate 100. Furthermore, a portion of the isolation structure 104 is disposed in the capacitor 102. The active devices 106a and 106b are disposed on the substrate 100. The active device 106b disposed on the capacitor 102 serves as a passing gate and the active device 106a disposed beside the capacitor 102 serves as a switching gate. The doped regions 108 are disposed in the substrate 100 on the respective sides of the active device 106a so that the active device 106a is electrically connected to the capacitor 102. Furthermore, the doped regions 108 can also serve as a source/drain region. The insulating layer 110 is disposed on the substrate 100 between the active device 106b and the capacitor 102. The contacts 112a and 112b are disposed on the substrate 100 such that the contacts 112a and the doped region 108 are electrically connected and the contacts 112b is electrically connected to the capacitor 102 after penetrating through the insulating layer 110.
However, the aforementioned disposition of the DRAM capacitor limits the level of device integration. In other words, the level of integration can hardly increase even if the technique for producing finer lines is continuously improved because of the aforementioned spatial constraint for the memory. As a result, fabricating more devices within a limited space and increasing the spatial utilization of a wafer is an issue that every semiconductor manufacturer concerns.